The present invention relates to a semiconductor memory device; and, more particularly, to a ferroelectric memory device, which employs as a data storage device a ferroelectric capacitor, obtained by using a ferroelectric material as a dielectric of the capacitor.
As is well known, since a capacitor made of a ferroelectric material serves to sense a variation in an electric charge induced by a voltage applied across the capacitor and accumulates the sensed value as data therein, it is being utilized as a nonvolatile memory device.
FIG. 1 is a connection diagram of a unit cell in a conventional ferroelectric memory device. In FIG. 1, two unit cells, each of which including a switching transistor 11 and a ferroelectric capacitor 12, are shown.
Referring to FIG. 1, the switching transistor 11 in one unit cell has its gate coupled to a wordline WL1 which controls the switching transistor 11, its source coupled to a bitline BL and its drain coupled to one end (i.e., storage electrode) of the ferroelectric capacitor 12. The other end of the ferroelectric capacitor 12 is coupled to a plateline PL. As with the conventional DRAM, a voltage at the plateline PL is a half line input voltage, i.e., Vcc/2.
In such a configuration, the plateline PL and an initial voltage of a node A, which corresponds to the storage electrode, maintain the Vcc/2 during a standby mode, respectively.
In such standby mode, however, the node A has a junction capacitance and a junction resistance to cause a leakage current. The leakage current allows a potential across the node A to be gradually decreased. The decrease in potential across the node A causes a potential difference across the ferroelectric capacitor 12, resulting in a decrease in the electric charge accumulated therein. To overcome such problems, used in the prior art is a technique which precharges the bitline BL by Vcc/2 and then subsequently turning the wordline WL on, to recover the potential across the node A to Vcc/2. Unfortunately, the prior art technique suffers from a drawback that a continuous vibration in the node A with small width entails a loss of the accumulated charge.
FIG. 2 is a pictorial representation showing the structure of a memory cell, which has been descented in a commonly owned Korean patent application, Korean Ser. No. 1997/051050.
Referring to FIG. 2, the memory cell includes a first switching transistor 21 having its gate coupled to a positive wordline WL1, and its source and drain coupled between a bitline BL and a node A respectively, a ferroelectric capacitor 22 coupled between the node A and the plateline PL, and a second switching transistor 23 having its gate coupled to a negative wordline WL1, and its source and drain coupled to the node A and the plateline PL respectively. Since the gate of the first switching transistor 21 is coupled to the positive wordline WL1 and the gate of the second switching transistor 23 is coupled to the negative wordline WL1 having opposite sign to the positive wordline WL1, these transistors are alternatively turned on.
That is to say, in the memory cell shown in FIG. 2, a voltage applied to the plateline PL, i.e., Vcc/2, is relayed to the node B at all times, and the negative wordline WL1 is activated during inactivation of the positive wordline WL1, to thereby prevent a potential difference across the ferroelectric capacitor 22 from being occurred.
However, various fashions have been applied in layout considerations of the memory cell with such structure, but a variety of defects are invoked in setting the ferroelectric capacitor in array.
Typically, the capacitor is disposed on top of an element isolation film (field oxidation film), which is used to separate between devices or cells. As such, a substantially increased step is incurred after the fabrication of the ferroelectric capacitor. In addition, the presence of a resistance at the node B prevents the same voltage as the plateline PL from being relayed to the node A acting as the storage electrode of the ferroelectric capacitor, resulting in a slight potential difference across the ferroelectric capacitor.
It is, therefore, a primary object of the present invention to provide a ferroelectric memory device, which is capable of preventing a potential difference across a ferroelectric capacitor from being occurred and minimizing a step to be induced during the fabrication of the ferroelectric capacitor.
In accordance with one aspect of the present invention, there is provided a ferroelectric memory device, comprising: a first switching transistor having its gate coupled to a positive wordline, and its source and drain coupled between a bitline and a first node respectively; a ferroelectric capacitor coupled between the first node and a plateline; a second switching transistor having its gate coupled to a negative wordline, and its source and drain coupled to the first node and the plateline respectively; wherein a second node at which the source of the second switching transistor and the plateline are contacted is formed on an active area locating between two adjacent negative wordlines; and the ferroelectric capacitor is formed on the active area.